The current marketed switching mode light emission diode (LED) driver is operated in a boundary current mode (BCM) and also has a closed loop circuit for locking a LED current. Referring to FIG. 1, FIG. 1A is a schematic diagram of a conventional switching mode LED driver. The conventional switching mode LED driver 1 comprises a current-to-voltage converter 11, an error amplifier EA, a compensation capacitor C_COMP, and a comparator CMP. The current-to-voltage converter 11 is connected to the error amplifier EA, and the error amplifier EA is connected to the compensation capacitor C_COMP and the comparator CMP.
The LED current iLED (i.e. the current passing through the LED) is fed back to the switching mode LED driver 1, and the current-to-voltage converter 11 receives the LED current iLED and converts the LED current iLED to the feedback voltage CS, wherein the LED current iLED is a triangle signal, and thus the feedback voltage CS is also a triangle signal. The error amplifier EA receives the feedback voltage CS and the reference voltage VREF, and then compares the feedback voltage CS with the reference voltage VREF to generate the error signal COMP accordingly. The compensation capacitor C_COMP is connected between the output end of the error amplifier EA and a ground GND, and used to compensate the error signal COMP. The comparator CMP compares the error signal COMP with a saw signal V_SAW to generate a pulse signal DUTY which is used to modulate the LED current iLED.
Referring to FIG. 1B, FIG. 1B is a schematic diagram of an error amplifier. The error amplifier EA comprises a current source IS, NMOS transistors MN1 through MN4, and PMOS transistors MP1 through MP4. Source ends of the PMOS transistors MP3 and MP4 are connected to a high voltage, such as a system voltage, gate ends of the PMOS transistors MP3 and MP4 are connected to each other, and drain ends of the PMOS transistors MP3 and MP4 are respectively connected to the gate end of the PMOS transistor MP3 and one end of the compensation capacitor C_COMP.
Source ends of the NMOS transistors MN1 through MN4 are connected to a low voltage, such as a ground voltage, gate ends of the NMOS transistors MN1 and MN3 are connected to each other, gate ends of the NMOS transistors MN2 and MN4 are connected to each other, drain ends of the NMOS transistors MN3 and MN1 are respectively connected to the drain end of the PMOS transistor MP3 and the gate end of the NMOS transistor MN1, and drain ends of the NMOS transistors MN4 and MN2 are respectively connected to the drain end of the PMOS transistor MP4 and the gate end of the NMOS transistor MN2.
Source ends of the of the PMOS transistors MP1 and MP2 are connected to the current source IS, gate ends of the PMOS transistors MP1 and MP2 respectively receive the feedback voltage CS and the reference voltage VREF, and drain ends of the PMOS transistors MP1 and MP2 are connected respectively to the drain ends of the NMOS transistors MN1 and MN2. The PMOS transistors MP1 and MP2 act as a differential pair circuit, and the NMOS transistors MN1 and MN2 act as an active load circuit.
The error amplifier EA should allow a large input differential signal formed by the feedback voltage CS and the reference voltage VREF. To make sure the error amplifier EA allows larger differential signals, the error amplifier EA should have a small transconductance Gm, and the differential pair circuit and the active load circuit should respectively have small transconductances Gm1 and Gm2. However, the mismatch (i.e. voltage offset Vos2) of the active load circuit is reflected to the input voltage offset Vos2′ of differential pair circuit, i.e. Vos2′=Vos2*Gm2/Gm1. So that, small Gm operating EA leads larger input offset.
To cure the deficiency of input voltage offset (i.e. reducing the input voltage offset), one manner is to increase the area of the error amplifier EA. However, in the current application, the reference voltage VREF of the conventional switching mode LED driver is required to be 200 mini volts with ±3 percent tolerance, and thus the small voltage offset is demanded.
Referring to FIG. 2A, FIG. 2A is a schematic diagram of a conventional compensation circuit for an input voltage offset of an error amplifier. The conventional compensation circuit 2 comprises a bandgap voltage generator 21, a trimming circuit 22, switches SW1, SW2, and a dimming control circuit 23. The bandgap voltage generator 21 is connected to the trimming circuit 22, the switch SW1 is connected to the trimming circuit 22 and the error amplifier EA, and the switch SW2 is connected to the dimming control circuit 23 and the error amplifier EA.
The bandgap voltage generator 21 is used to generate a bandgap voltage to the trimming circuit 21. The trimming circuit 21 has resistors R1 through R4 which are connected serially, and further has fuses F1 and F2, wherein the fuse F1 is parallel connected to resistor R2, and the fuse F2 is parallel connected to resistor R3. The connection point of the resistors R2 and R3 is connected to the error amplifier EA, so as to provide the reference voltage VREF to the error amplifier EA.
The bandgap voltage is input to the trimming circuit 21. While the input voltage offset Vos does not exist, the fuses F1 and F2 are not fused, such that the reference voltage VREF is the dividing voltage of the bandgap voltage divided by the resistors R1 and R4. While the input voltage Vos exists, at least one of the fuses F1 and F2 is fused, and the reference voltage VREF is the dividing voltage of the bandgap voltage divided by the resistors “R1, R2, R4”, “R1, R3, R4”, or “R1 through R4”, so as to compensate the input voltage offset Vos. For example, while the required reference voltage VREF is 200 mini volts, and the input voltage offset Vos is −20 mini volts, to compensate the −20 mini volts, at least one of the fuses F1 and F2 is fused, and thus the actual reference voltage VREF is increased to 220 mini volts.
The switch SW1 is turned on while the dimming function is not enabled, and thus the reference voltage VREF which the input voltage offset Vos has been compensated is input to the error amplifier. The switch SW2 is turned while the dimming function is enabled. The dimming control circuit 23 has an analog dimming ratio curve defining the relation of an input analog signal AND and the reference voltage VREF, and thus the dimming control circuit 23 converts the input analog signal AND to the reference voltage VREF based upon the analog dimming ratio curve.
Referring to FIG. 2B, FIG. 2B is a curve diagram of an analog dimming ratio curve. The ideal analog dimming ratio curve of the dimming control circuit 23 is shown in FIG. 2B. However, the input voltage offset Vos exists, and thus the analog dimming ratio curve is shifted upward or downward due to the input voltage offset Vos. That is, the trimming circuit 21 cannot give help to the dimming control circuit 23, and the dimming control circuit 23 should adjust the ideal analog dimming ratio curve to deal with the input voltage offset Vos.
It is noted that for the analog dimming as shown in FIG. 2A and FIG. 2B, the actual reference voltage VREF for dimming can be expressed as VREF=(AND−0.2)+Vos. Furthermore, while pulse width modulation (PWM) dimming is used instead, the input voltage offset Vos still affects the PWM dimming, and the actual reference voltage VREF for dimming can be expressed as VREF=(VREFIDEAL+Vos)*DUTY, wherein the ideal reference voltage is denoted as VREFIDEAL, and the duty cycle is denoted as DUTY. In short, the above trimming manner for compensating input voltage offset cannot be applied in the dimming function.
There are other marketed compensation circuits for input voltage offsets of error amplifiers. However, in each of the above marketed compensation circuits, the current source of the error amplifier should be the same as the compensation current source, the biasing current should be known before compensation, and the more than two transistors in the compensation circuit should designed to be matched. Unfortunately, the biasing current shifted with the process variation is not known easily, and the design for matching more than two transistors is not easy, either.